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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 2-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
Interface 2 (I2S2)
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D8]/
I2S2_CLK/
GP[18]/
SPI_CLK
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
P12
N10
N11
P11
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 transmit data output I2S2_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 clock input/output I2S2_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 receive data input I2S2_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For I2S, it is I2S2 frame synchronization input/output I2S2_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Interface 3 (I2S3)
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
P14
N12
N13
P13
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 transmit data output I2S3_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 clock input/output I2S3_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 receive data input I2S3_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 frame synchronization input/output I2S3_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Copyright ? 2010–2013, Texas Instruments Incorporated
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